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Preliminary
SC3015B
?
Quartz SAW Frequency Stability
?
?
?
?
Fundamental Fixed Frequency
Very Low Jitter and Power Consumption
Rugged, Miniature, Surface-Mount Case
Low-Voltage Power Supply (3.3 VDC)
550.0 MHz
Differential
This digital clock is designed for use with high-speed CPUs and digitizers. Fundamental-mode oscillation is
made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size,
and low power consumption. Differential outputs provide a sine wave that is capable of driving 50 Ω loads.
Absolute Maximum Ratings
Sine-Wave
Clock
Rating
Power Supply Voltage (V CC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Electrical Characteristics
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8B Case
Characteristic
Sym
Notes
Minimum
Typical
Maximum
Units
Output Frequency
Q and Q Output
Absolute Frequency
Tolerance from 400.000 MHz
Voltage into 50 Ω (VSWR ≤ 1.2)
Operating Load VSWR
f O
Δ f O
V O
1, 2
1, 3
549.89
0.60
550.0
550.11
±200
1.1
2:1
MHz
ppm
V P-P
Symmetry
Harmonic Spurious
Nonharmonic Spurious
3, 4, 5
3, 4, 6
49
51
-30
-60
%
dBc
dBc
Q and Q Period Jitter
Output (Disabled)
No Noise on V CC
200 mV P-P from 1 MHz to ? f O on
Amplitude into 50 Ω
3, 4, 6, 7
3, 4, 7, 8
3, 9
15
30
35
75
ps P-P
ps P-P
mV P-P
Output DC Resistance (between Q & Q)
3
50
K Ω
ENABLE (Terminal 14) Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
V IH
V IL
I IH
I IL
t PD
3, 9
V CC -0.1
0.0
V CC
3
V CC +0.1
0.20
5
-1
1
V
V
mA
mA
ms
DC Power Supply
Operating Voltage
Operating Current
V CC
I CC
1, 3
+3.13
+3.30
20
+3.47
40
VDC
mA
Operating Ambient Temperature
T A
1, 3
0
+70
°C
Lid Symbolization (YY = Year, WW = Week)
RFM SC3015B 550.00 MHz YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
2.
3.
4.
5.
Unless otherwise noted, all specifications include any combination of load
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to
ground. (See: Typical Test Circuit.)
One or more of the following United States patents apply: 4,616,197; 4,670,681;
4,760,352.
The design, manufacturing process, and specifications of this device are subject
to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
6.
7.
8.
9.
Jitter and other spurious outputs induced by externally generated electrical noise
on V CC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
Applies to period jitter of Q and Q. Measurements are made with the Tektronix
CSA803 signal analyzer with at least 1000 samples.
Period jitter measured with a 200 mV P-P sine wave swept from 1 MHz to one-half
of f O at the V CC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
www.RFM.com E-mail: info@rfm.com
?2008 by RF Monolithics, Inc.
Page 1 of 2
SC3015B - 3/27/08
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